Integrated circuits fabricated in silicon-on-insulator substrates offer performance advantages including freedom from latchup for CMOS structures, high packing density, low parasitic capacitance, low power consumption, radiation hardness, high voltage operation, and the possibility of three dimensional integration. Indeed, isolation trenches extending through the silicon layer down to the insulation provide a simple approach to dielectric isolation of integrated circuit devices. The sidewalls of such trenches are coated with an insulator, usually silicon dioxide, and the remaining portion of trench opening, if any, is filled with a filler, usually polycrystalline silicon. Diffused PN junctions can also be used for lateral isolation.
Additionally, silicon-on-insulator technology using very thin films offers special advantages for submicron devices. Scaling bulk devices tends to degrade their characteristics because of small-geometry effects such as punch-through, threshold voltage shift, and subthreshold-slope degradation. The use of silicon-on-insulator devices suppresses these small-geometry effects. Therefore, even in the submicron VLSI domain, silicon-on-insulator technology can offer even higher device performance over bulk technology, along with the inherent advantages of silicon-on-insulator.
Silicon-on-insulator substrates may be fabricated in various ways: a crystalline silicon layer may be formed over an existing oxide layer either by laser or strip heater recrystallization of polysilicon deposited on the oxide, or by selective epitaxial silicon growth over the oxide. However, the quality of such a silicon layer is generally inferior to that normally associated with bulk silicon. Other approaches entail forming an oxide layer beneath an existing high quality silicon layer, either by oxidizing a buried porous silicon layer or by oxygen ion implantation; however, such oxide is low quality, and the silicon top layer may be damaged during the oxide layer formation.
Another approach to silicon-on-insulator is wafer bonding, as described by J. Lasky et al., “Silicon-On-Insulator (SOI) by Bonding and Etch-Back,” 1985, IEDM Tech. Deg., 684. This wafer bonding process proceeds as follows: a lightly doped epitaxial layer of silicon is grown on a heavily doped silicon substrate, oxide is thermally grown on the epitaxial layer, a second lightly doped silicon substrate is thermally oxidized, and the two oxidized surfaces are pressed together. See FIG. 1a. The pressed together wafers are inserted into an oxidizing atmosphere at 1100° C. to bond them, as illustrated in FIG. 1b. Lastly, a preferential etch is used to remove the heavily doped substrate, leaving the thin, lightly doped epitaxial layer above the bonded thermally grown oxides, which are now on the second substrate, as shown in FIG. 1c. The resulting thin silicon layer above the thermally grown oxide is of high quality; the oxide also retains its quality and may be either thick, as might be desired for CMOS or high voltage devices, or thin, as might be desired for shared element applications. FIG. 1d heuristically illustrates trench isolation with polysilicon-filled trenches isolating MOSFET and bipolar devices.
Conceptually, this process may meet all the desired goals for the ultimate silicon-on-insulator material: a specular finished crystalline silicon layer without dislocations and a back interface with the insulator of quality equal to the interface of thermally grown silicon dioxide on silicon, both the crystalline silicon layer and the insulator being of variable thickness.
Another wafer bonding method, illustrated in FIGS. 2a-c and described in U.S. Pat. No. 5,362,667, proceeds as follows: Beginning with a device wafer having a lightly doped epitaxial layer on a heavily doped substrate and a handle wafer with a thick (4,000 A) oxide layer, activate the device wafer surface with an acid or peroxide wash to enhance hydroxyl group formation. Place a drop of oxidant such as water plus hydrogen peroxide on the oxide, and squeeze the wafers together. See FIG. 2a. The drop of oxidant has a volume in the range of 0.8 to 8.0 microliters per square inch of wafer surface. After drying the squeezed wafers at room temperature for a day, heat them to 1150° C. for two hours, which causes oxidation of the device wafer and formation of silicon-oxygen bonds to fuse the wafers. See FIG. 2b. Lastly, grind and etch the device wafer to expose the epitaxial layer, which completes the silicon-on-insulator substrate, as shown in FIG. 2c. For applications that require a thick (10-60 μm) silicon-on-insulator layer and a thicker (e.g., 4 μm) bottom oxide but allow some tolerance in the layer thickness, a slightly simpler process, where a uniformly lightly doped device wafer is thinned by grinding and polishing, can be used.
Bonded wafers, however, have problems of high temperature bonding that lead to film stress and delamination. Also, because oxides are poor diffusion barriers to mobile ions such as sodium, bonded wafers with silicon dioxide buried layers are susceptible to contaminant diffusion. Contaminants introduced during the bonding process can easily diffuse to the device layer interface, resulting in electrical instability.